Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

You will own the digital architecture and implementation of the high‑bandwidth memory (HBM) base die, from micro‑architecture through silicon bring‑up.
Your work directly impacts bandwidth, latency, power, and reliability for a complex mixed‑signal system.
You will collaborate across design, verification, physical design, and test teams to deliver first‑pass silicon success.

Responsibilities will include, but are not limited to:

Define and own micro‑architecture for base‑die digital subsystems, including high‑bandwidth memory (HBM) channel support logic, boot and initialization sequencing, training orchestration, configuration and status registers (CSR), telemetry, performance counters, and reliability features.
Translate system requirements into timing, power, and area budgets by partnering with physical layer (PHY) and system architects, and maintain clear interface specifications for bus protocols, clock‑domain crossing (CDC), and reset strategy.
Implement and integrate synthesizable register‑transfer level (RTL) designs in SystemVerilog, including multi‑channel logic, interrupts, events, register maps, scan hooks, and design‑for‑test (DFT) interfaces.
Ensure robust reset and power‑up behavior, handle corner cases, and maintain clear engineering change order (ECO) pathways.
Collaborate with design verification (DV) teams to build verification plans, achieve coverage goals, complete CDC and reset‑domain crossing (RDC) checks, and debug RTL, testbench, and gate‑level issues.
Provide guidance on timing constraints, exceptions, and path intent, and refine micro‑architecture to resolve timing‑critical paths.
Partner with DFT and test teams to integrate scan, memory built‑in self‑test (MBIST), logic built‑in self‑test (LBIST), boundary access, and debug instrumentation.
Support post‑silicon validation by enabling debug hooks, correlating issues to RTL or architecture, and driving efficient issue resolution.

Minimum Qualifications:

Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
Typically 10+ years of experience in digital design or system‑on‑chip (SoC) integration with ownership of complex logic through tape‑out.
Expertise in SystemVerilog RTL design, clock and reset architecture, clock‑domain crossing (CDC) and reset‑domain crossing (RDC) methodologies, and low‑power design concepts.

Our vision is to transform how the world uses information to enrich life for all.

Responsibilities will include, but are not limited to:

Define and own micro‑architecture for base‑die digital subsystems, including high‑bandwidth memory (HBM) channel support logic, boot and initialization sequencing, training orchestration, configuration and status registers (CSR), telemetry, performance counters, and reliability features.
Translate system requirements into timing, power, and area budgets by partnering with physical layer (PHY) and system architects, and maintain clear interface specifications for bus protocols, clock‑domain crossing (CDC), and reset strategy.
Implement and integrate synthesizable register‑transfer level (RTL) designs in SystemVerilog, including multi‑channel logic, interrupts, events, register maps, scan hooks, and design‑for‑test (DFT) interfaces.
Ensure robust reset and power‑up behavior, handle corner cases, and maintain clear engineering change order (ECO) pathways.
Collaborate with design verification (DV) teams to build verification plans, achieve coverage goals, complete CDC and reset‑domain crossing (RDC) checks, and debug RTL, testbench, and gate‑level issues.
Provide guidance on timing constraints, exceptions, and path intent, and refine micro‑architecture to resolve timing‑critical paths.
Partner with DFT and test teams to integrate scan, memory built‑in self‑test (MBIST), logic built‑in self‑test (LBIST), boundary access, and debug instrumentation.
Support post‑silicon validation by enabling debug hooks, correlating issues to RTL or architecture, and driving efficient issue resolution.

Minimum Qualifications:

Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
Typically 10+ years of experience in digital design or system‑on‑chip (SoC) integration with ownership of complex logic through tape‑out.
Expertise in SystemVerilog RTL design, clock and reset architecture, clock‑domain crossing (CDC) and reset‑domain crossing (RDC) methodologies, and low‑power design concepts.

Mixed Signal Design Engineer , HBM

Responsibilities will include, but are not limited to:

Minimum Qualifications:

Mixed Signal Design Engineer , HBM

Responsibilities will include, but are not limited to:

Minimum Qualifications:

Preferred Qualifications:

Micron Technology

Micron Technology

Benefits

Micron Technology