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Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such as physical design, STA, DFT, and packaging? Have you taped out so many chips that you can identify potential design problems hidden in EDA reports, advise design teams on how to fix them and then publish an application note about avoiding them in future? Do you love technical-deep-dive with engineers and providing an eagle’s eye summary to management? If this is your engineering profile and you are looking for a challenge, then we have one for you.
Broadcom develops critical Infrastructure chips that enable a variety of Customers to produce ASICs in almost all major segments of the Semiconductor industry, including AI. Our ASIC products division is looking for a senior engineer to guide Customer teams designing challenging chips in areas such as AI, HPC, networking and storage. This is an immensely responsible position, and an opportunity to push the frontiers of technology by working with cross-functional teams inside and outside of Broadcom.
As a valued member of this team, you will be required to do the following:
Manage external customer ASIC programs from inception to finish, including RFQs, technology and IP collaterals, design, test, packaging, fabrication, bring-up and production
Advise customers on best practices in EDA, flows and design methodologies, and by organizing Q&A sessions with Broadcom technology experts
See ahead, plan ahead, work ahead. Proactively assess potential risks to the design quality, project schedule, then work with cross-functional teams to prepare and execute risk mitigation actions
Execute physical design flows to check that incoming customer tape-in netlists meet Broadcom’s stringent tape-out quality standards
Motivate and drive yourself to stay abreast of developments in Broadcom IPs, technology and end user applications
Participate in discussions about your chips with marketing, sales, legal and regulatory compliance teams
Be a consummate team player and assist other teams in need
You must have these proven skills to qualify for this position:
Multiple tape-outs in advanced technology nodes
Analyze PPA tradeoffs involved amongst various library components, and architectures
Knowledgeable in low power design and power management
Hands-on experience in physical design and STA, EDA tools, design flows for physical design, logic simulation, test, and packaging
Programming in TCL, shell and scripting languages
Following skills are nice to have:
Exposure to SERDES communications protocols.
Logic design, chip architecture, microarchitecture, Verilog RTL coding Front-end logic design verification, DRC, logic synthesis
Knowledge of DFT methods including scan, memory BIST and repair
Education and Experience required:
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $163,800 - $262,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
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