Determines methods and procedures on new assignments, and provide guidance to subcon engineering teams and other colleagues.
Support customer compliant and audit report.
Engineering support on customer information request.
Co-work with Design and SQE on setting up wafer process flow, control plan, FMEA and other APQP documents.
Manage wafer acceptance test (WAT) programs and specifications, drive wafer processing and coordinate assembly& package for production yield improvement
Representative of Semtech Protection BU in low yield / non-confirming material data analysis, failure analysis, disposition and driving yield improvement.
Job Requirement:
EXPERIENCE: More than 5 years’ experience in wafer PIE or fab TD positions. Candidates come with assembly and test experience is preferred. Well know traditional package process such as WLP, QFN, QFP, SOT, etc.
KNOWLEDGE: Well knowing discrete assembly process and devices physics, esp. for power diode, SCR, power MOSFET, SBD and other power discrete. Good understanding of semiconductor device failure analysis method and reliability failure mechanism. Having sense of advanced assembly &package, and WAT, Sample probe test and final test. Understanding ESD, Surge and TLP, temperature bias, voltage bias, and other Char test mechanism. Experience on data analysis tools, e.g. JMP, Datapower. Familiar with MS office.
Communication skill: Good command of written and spoken English and Chinese.
JOB COMPLEXITY: Works on complex issues where analysis of situations or data require an in-depth evaluation of variable factors. Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results. Internal and external contacts often pertain to company plans and objectives.
SUPERVISION: Report to Sr. Fab Engineering Manager in China. Dot line to Yield Engineering Manager in CO, USA.
Education: Major of Semiconductor Physics or Semiconductor Devices is required, and M.S. degree or above is preferred.
