Senior Principal Physical Design Engineer

Senior Principal Physical Design Engineer

Job Summary

As a Senior Principal Physical Design Engineer, you will be a key technical leader responsible for driving and executing advanced physical design activities for complex SoC and IP blocks. You will play a pivotal role in achieving challenging performance, power, and area targets for cutting-edge semiconductor products.

Job Responsibilities

• Lead and execute all aspects of physical design for large-scale digital designs from RTL to GDSII, including floor planning, power planning, place and route, clock tree synthesis, static timing analysis (STA), formal verification, design rule checking (DRC), and layout versus schematic (LVS).
• Drive and optimize design methodologies, flows, and scripts to improve efficiency, turnaround time, and design quality.
• Perform critical path analysis and provide innovative solutions to meet aggressive frequency and power targets.
• Collaborate closely with design, architecture, and verification teams to ensure robust design implementation and resolve complex technical issues.
• Mentor junior and mid-level engineers, providing technical guidance and fostering their growth within the physical design domain.
• Evaluate and integrate new EDA tools and technologies to enhance physical design capabilities.
• Contribute to defining and reviewing design specifications and architecture documents from a physical implementation perspective.
• Develop and implement low-power design techniques (e.g., clock gating, power gating, multi-voltage design) to achieve challenging power budgets.
• Generate comprehensive reports and documentation throughout the design cycle.

Job Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.

• 15+ years of extensive experience in ASIC physical design with a strong track record of successful tape-outs on advanced process nodes.

• Deep expertise in industry-standard EDA tools for physical design (e.g., Cadence Innovus/Tempus, Synopsys Fusion Compiler/PrimeTime, Ansys RedHawk/PathFinder).

• Proficiency in scripting languages (Tcl, Perl, Python) for automation and flow development.

• Strong understanding of static timing analysis concepts, constraints, and methodologies.

• Hands-on experience with low-power design techniques and methodologies.

• Solid understanding of semiconductor physics, process technology, and DFM (Design for Manufacturability) principles.

• Demonstrated ability to lead technical initiatives and mentor other engineers.