Senior Foundry Engineer, Silicon Technology

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

We are seeking a Senior Foundry Engineer, Silicon Technology to support foundry engagement, silicon-to-model correlation, tapeout readiness, and yield improvement for advanced semiconductor products. This person will work closely with internal design, CAD layout, product engineering, test, reliability, operations teams and external foundry partners to identify risks, assess product impact, and drive timely resolution of process, PDK, model, DRC/DFM, and silicon-related issues.

Responsibilities Include

• Silicon, process and yield correlation
  • Analyze process inline data, silicon test data, process drift and process correlation data
  • Fine tune processes to optimize power, performance and yield
  • Help identify process related contributors to parametric drift, yield loss, leakage, reliability risk
  • Work with foundry and internal teams to investigate yield issues and process excursions
  • Perform layout analysis where needed to understand process sensitivity, failures
• Tapeout and DFM support
  • Support product tapeouts, tapeout readiness reviews from a PDK, DRC/DFM, device model and reliability perspective
  • Run or coordinate DFM checks on products and summarize findings for design and layout teams
  • Coordinate between foundry and physical design teams to disposition waivers taking performance, leakage, manufacturability and reliability in mind
  • Document known PDK, model, DRC, DFM or process risks before tapeout
  • Maintain an internal PDK qualification database across foundries and process nodes to reduce tapeout risk from unnoticed PDK or model changes
• Foundry and PDK support
  • Support technical interactions with foundry partners on PDK, device models, process assumptions, design rules, DRC/DFM decks and reliability collateral